For the supporting of the experiments at GSI a completely new data acquisition system is developed in Experiment-Electronics Department of GSI. The main hardware component of the system is a FEBEX module with 14-bit pipe-lining ADC (50 MHz or 100 MHz).

Its VHDL core features a “self-triggering” (programmable Fast Trapezoidal Filter for hit finding), hit’s energy measurement (programmable Energy Trapezoidal Filter) and block data transfer via optical link with 2 G-bit per second speed (GOSIP interface).

The FEBEX boards are designed to work with globally triggered DAQ systems by accepting user defined trigger windows.
 

FEBEX 3:

Publications:

New TASCA Data Acquisition Hardware Development for the Search of Element 119 and 120

Febex Data Acquisition System

Manuals:

Febex 3 board as LVDS IO Register (4 bit)

Febex 3 board as LVDS IO Register (8 bit)Febex 3 control and configuration registers

Febex 3 and 4: Initialization of MCP443X/5X chip (CALIFA board)

FEBEX 4:

Publications:

FPGA Hit Finder and Energy Filter for the FEBEX Pipelining ADC

Manuals:

Febex 4 control and configuration registers

Febex 4 Initialization for APFEL chip (via GOSIP)